1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device capable of performing a burn-in test of a memory using a memory self-test circuit.
2. Description of the Related Art
Conventionally, in a burn-in test of a memory with an embedded system LSI, in order to achieve a burn-in test of both of the memory and a logic circuit at the same time and cope with limitation of the controllable number of terminals in a jig used for burn-in, measures for reducing the number of terminals used for memory control have been made.
For example, as disclosed in Japanese Patent Publication Laid-Open No. 11-260096 (Reference No. 1), test data, an address, and a memory control signal required for a test of the memory are generated using a frequency dividing output signal of an address generation circuit which is a frequency divider of an external clock, and a pass/fail signal of a test result is produced as a pass/fail judgment flag signal, thereby enabling a test of a memory macro with two pins of the combined use of an input pin and an output pin, and enabling a simultaneous test of a memory section and a logic circuit section at the time of a burn-in test.
However, in a burn-in test of the memory circuit disclosed in the above Reference No. 1, a generation circuit for generating test data, an address signal, and a memory control signal required inside the memory as a test circuit, and a pass/fail signal judgment circuit of the test result are required, so that it has a technical problem that a circuit area of a memory section increases due to a test circuit section which is not directly related to an actual operation of the memory.
In the meanwhile, with an improvement in speed of a memory section and an increase in the number of memory macros mounted in one chip in recent years, a request for implementation of an at-speed test, a reduction in the number of external terminals, or the like has been increased. Therefore, in order to satisfy the request described above, a system LSI which mounts a functional circuit (memory BIST (Built In Self Test) circuit) for performing a self-test of the memory in a chip has been increased.
Generally, as the operation of the memory BIST circuit, the memory section is tested with a certain specific test pattern, and a pass/fail signal of the test result is produced after the test is completed, so that a pass/fail judgment of the memory is performed.
As a problem that this memory BIST circuit is applied to the burn-in test of the memory, the test pattern of the memory section during the burn-in is included. It is necessary to continuously provide the test pattern for the memory section during the burn-in test of the memory. However, since the memory BIST circuit stops the test to the memory section after the test is completed, it is necessary to reset the memory BIST circuit and restart the test. Specifically, it has had a technical problem that a control of a reset operation from the outside has been needed whenever the memory BIST test has been completed, and a technical problem that external terminals for reset control have increased in number in the burn-in test of the memory.